A 10,000 Frames/s 0.18 μm CMOS Digital Pixel Sensor with Pixel-Level Memory

In a Digital Pixel Sensor (DPS), each pixel has an ADC, all ADCs operate in parallel, and digital data is directly read out of the image sensor array as in a conventional digital memory [1]. The DPS architecture offers several advantages over analog image sensors including better scaling with CMOS technology due to reduced analog circuit performance demands and the elimination of column fixed-pattern noise and column readout noise. With an ADC per pixel, massively parallel conversion and high-speed digital readout become possible, completely eliminating analog readout bottlenecks. This benefits traditional high speed imaging applications and enables new imaging enhancement capabilities such as multiple sampling for increasing sensor dynamic range [2]. Achieving acceptable pixel sizes using DPS, however, requires the use of a 0.18 μm or below CMOS process, which is challenging due to reduced supply voltages and increased leakage currents [3].